As semiconductor processing technology advances, the feature sizes of devices in a semiconductor memory integrated circuit become smaller, the operating speed of the devices becomes faster while the power consumption is reduced. In semiconductor devices at nanometer scales, variations in process, supply voltage, temperature (PVT), and other adverse factors may cause various deviations of the same transistor from the original design. The process deviation has a significant impact on a device performance and increases the difficulty level of a complete circuit simulation. Process variations cause different memory cells to have different speeds for write and read operations, resulting in timing inconsistency. Variations in supply voltage and temperature may further cause timing differences which adversely affects the correct read and write operations of a memory.
Static random access memories (SRAMs) are widely used as volatile memory in computers, mobile phones and other electronic products. In general, the SRAM read speed is slower than the write speed, thus, more attention is paid to tracking the timing of the data read path. As the integration level and power consumption requirements are higher, the supply voltage also decreases. At lower supply voltages, the SRAM write speed also decreases, in addition to the worst case process condition, if the data write delay is not considered, the effective time of the signal available on a word line or bit line may not be sufficient to complete a write operation successfully, ultimately resulting in a lower yield of the SRAM. Therefore, there is a need for a novel write tracking circuit to improve the timing accuracy and reliability of an SRAM.